1. Field of the Invention
The present invention relates to a semiconductor memory device for outputting data at a high speed synchronized to a clock.
2. Description of the Related Art
In some semiconductor memory devices, data exchanges can take place during both rise and fall of the pulse signals of a system reference clock. This type of semiconductor memory device divides input/output data internally into two phases of the clock pulse, a rise phase and a fall phase, so that data in each phase are processed internally at twice the period of the external data period, thus enabling an apparently high internal processing speed to be consistent with highspeed serial data transfer.
FIG. 10 shows a schematic diagram of a conventional configuration of such a semiconductor memory device, in which serial data synchronized to a reference clock are processed through an input/output (i/o) pad 100, which is for connection to an external environment. The reference clock is a system reference clock in the system including this semiconductor memory device. Serial data exchanged with the external environment are processed one bit at time at the rise and fall phases of each clock pulse in the memory device. In general, data processed during the rise phase of the pulses are called even data, and data processed during the fall phases of the pulses are called odd data (these expressions will be used in the following presentation).
A demultiplexer 101 separates serial write-data input via the i/o pad 100 into even data and odd data according to the system reference clock CLK. The demultiplexer 101 supplies even data to serial-parallel conversion circuits 102-1e, 102-2e, and odd data to serial-parallel conversion circuits 102-1o, 102-2o.
Serial-parallel conversion circuits 102-1e, 102-2e and 102-1o, 102-2o supply parallel data outputs to respective write-amps 103-1, 103-2, which enter the data to respective memory cells in the memory cell arrays 104-1, 104-2. These serial-parallel conversion circuits and write-amps are controlled according to into which of the memory cell arrays the data are to be entered. When the data are to be entered into memory cell array 104-1, only the serial parallel conversion circuit 102-1e, 102-1o and write-amp 103-1 are operated while, when the data are to be entered into memory cell array 104-2, only the serial parallel conversion circuit 102-2e, 102-2o and write-amp 103-2 are operated.
Data output from the memory cell arrays 104-1, 104-2 are amplified by respective data-amps 105-1, 105-2 for amplifying data to be supplied to parallel-serial conversion circuits 106-1e, 106-2e and 106-1o, 106-2o. The output data are parallel data constituted by the even data and odd data entered by the write-amps, and even data are supplied to parallel-serial conversion circuits 106-1e, 106-2e while odd data are supplied to parallel-serial conversion circuits 106-1o, 106-2o. A multiplexer 107-e selects and outputs even data output from parallel-serial conversion circuits 106-1e or 106-2e, while a multiplexer 107-o selects and outputs odd data output from 106-1o or 106-2o.
These data-amps, parallel-serial conversion circuits and multiplexers are controlled according to which of the memory cell arrays is to be used for reading the data. That is, when the data are to be read from the memory cell array 104-1, only the data-amp 105-1 and the parallel-serial conversion circuits 106-1e and 106-1o are operated so that the multiplexers 107-e, 107-o select data output from the parallel-serial conversion circuits 106-1e, 106-1o and output those data respectively. On the other hand, when the data are to be read from the memory cell array 104-2, only the data-amp 105-2 and the parallel-serial conversion circuits 106-2c and 106-2o are operated so that the multiplexers 107-e, 107-o select data output from the parallel-serial conversion circuits 106-2e, 106-2o and output those data respectively. Operational control for such read steps and above write steps is carried out by a control circuit (not shown) by supplying appropriate control or selection signals (for example, the selection signals "U/L" indicated in FIG. 10) according to read/write addresses.
A multiplexer 108 outputs even data from the multiplexer 107-e during the rise phase of the system reference clock CLK, and outputs odd data from the multiplexer 107-o during the fall phase of the system reference clock CLK. Output data from the multiplexer 108 are output externally from the i/o pad 100.
According to such a device structure, when write-data are input into the i/o pad 100, data are divided in the demultiplexer 101 into even data and odd data, and the divided data are supplied to the respective serial-parallel conversion circuits. If the specified write address is in the memory cell array 104-1, inside the semiconductor memory device, even data are accepted by the serial-parallel conversion circuit 102-1e during the fall phases of the reference clock while odd data are accepted in the serial-parallel conversion circuit 102-1o during the rise phases of the reference clock. (It should be noted that, inside the memory device, there is no restriction regarding processing of even and odd data during the rise or fall phase of the clock pulse, so that such inversion of the timing of data exchange is allowable. Such method can be used for read-operations.) Accordingly, even data and odd data are converted to parallel-data, and are entered through the write-amp 103-1 into specific memory cells in the memory cell array 104-1.
When the data are to be read, data from appropriate memory cells corresponding to read addresses are supplied to the data-amp. If the specified read address is in the memory cell array 104-1, parallel even data and odd data from the memory cell array 104-1 are output to parallel-serial conversion circuits 106-1e, 106-1o through the data-amp 105-1 for conversion to serial data and the converted data are supplied to the multiplexers 107-e, 107-o. That is, even data are successively supplied to the multiplexer 107-e while being synchronized to the fall phases of the reference clock, and odd data are successively supplied to the multiplexer 107-o while being synchronized to the rise phases of the reference clock.
Then, multiplexers 107-e, 107-o select data from the respective parallel-serial conversion circuits 106-1e, 106-1o for outputting to the multiplexer 108, which selects data alternately during the rise or fall of the system reference clock pulses for successive data output. Accordingly, highspeed serial data are output externally one bit at a time during either the rise or fall of the reference clock pulses from the i/o pad 100. It should be noted that, in the memory cell array 104-2, processes similar to those described for the memory cell array 104-1 are carried out for the read/write data.
In recent years, increased circuit density of LSI devices has caused the operational speed of CPU to increase so that the system clock now operates at a speed exceeding 400 MHz. In contrast, although the capacity of semiconductor memory device has been increased, the resulting increase in the length of internal lines (for example, word lines, bit lines, and the like) causes an increase in the duration of charging/discharging the lines, thus slowing the response speed of the memory device so that the operational speed cannot be improved to the extent achievable in CPU circuits. In such semiconductor memory devices, it is essential that the slower internal processes be made compatible with the faster external data i/o processes to compensate for the difference in the longer operational cycle of the internal devices and shorter cycles of the external devices.
In such a situation, the conventional semiconductor memory devices described above can achieve an internal processing cycle that is double the processing cycle of the highspeed data i/o cycle by dividing the i/o data into two phases between the aft-stage of the demultiplexer and the fore-stage of the multiplexer. For this reason, it is necessary to position the input circuits (including demultiplexer 101) and output circuits (including multiplexers 107-e, 107-o and 108) close to the i/o pad 100, which serves as the boundary between the interior and exterior of the semiconductor memory device.
On the other hand, it is general that the i/o pads are placed close to the periphery of the chip, in which the semiconductor memory device is packaged in a resin, and the i/o pads are connected to the corresponding external lead terminals positioned at the periphery of the chip by wire bonding. However, in most layouts of the memory devices requiring a high capacity and high speed, i/o pads are arranged near the central band-like region (which will be referred to as the central region) of the memory package, and the memory cell arrays are placed on both lateral regions of the central region. High capacity memories nearly always follow such a dual-in-line package design.
Also, miniature packaging is demanded for the semiconductor memory device, and the device is often assembled into a chip size package (CSP) such as ball grid array (BGA). In the BGA package, i/o pads are arranged in the central region to correspond with a group of ball contacts, made of solder and the like, that are arranged in a grid pattern near the center area of the back of the packaging. When it is desired to minimize re-designing of an existing device to increase the memory capacity or to increase the data width for such BGA packaging, it is preferable to retain the existing configuration of address and data terminals so that the additional address and data terminals would be placed in the outer region of the existing terminals. Further, ball arrangement and their terminal assignments (to which i/o pads they will be connected) as well as the capacitance and inductance of each electrode are pre-determined in the specification concerning the semiconductor memory device, so a method of wiring from the ball grid is also specified. For these reasons, it is inevitable also from the structural viewpoint that the position of the i/o pads is chosen close to the central region.
Also, control circuits for peripheral circuits are also provided in the central region because of similar restrictions and their functional requirements. In such a case, if the i/o pads are located in the center line of the central region of the chip and the control circuits are placed on the lateral regions of the center line, data transfer in the control circuits must be performed by detouring the i/o pads, so that the circuit complexity increases considerably, and moreover, i/o pads must be spaced apart to allow for those interconnection lines. For this reason, circuits in semiconductor memory devices are laid out so that control circuits can be grouped to the one side or the other side of the central region so that the i/o pads can be placed on the opposing side so that the memory cell arrays are laid out on both outer regions of the central region of the memory chip.
Therefore, input/output (i/o) circuits (the above-mentioned input circuits and output circuits) that should be placed near the i/o pads are placed away from the center line of the memory chip. Accordingly, the path lengths of the lines from the i/o circuits to memory cell arrays on both outer regions are different, so that output data (read-data) from memory cell arrays that are distant from the i/o circuits are delayed in arriving at the output circuits. For example, in FIG. 10, if the i/o pad 100 is disposed closer to memory cell array 104-1 within the central region, parallel-serial conversion circuits 106-1e, 106-1o are relatively close to the output circuit (such as multiplexer 107-e), but the parallel-serial conversion circuits 106-2e, 106-2o are located further away, and read-data from memory cell array 104-2 take longer to arrive at the output circuit.
The difference in the arrival times of read-data to propagate from memory cell arrays to output circuit is of the order of 0.1 ns, when the system clock is operating at 400 MHz in a memory device having a width of the central region at 1500 .mu.m and the output circuit is placed within the central region at a width ratio of 1200:300 .mu.m. This order of time difference is not particularly serious when the data which have already been entered in the parallel-serial conversion circuits are to be output successively during the subsequent rise and fall phases.
However, for the lead-bit data (data of the bit to be sent first to the output circuit) for a read step, the lead-bit data must arrive at the output circuit synchronously with the first rise or fall phase of the system clock for the read step, including the time required to pass through the data-amp and parallel-serial conversion circuit. Therefore, when the read-data are located in the distant memory cell array, device operational speed is reduced. For this reason, in conventional semiconductor memory devices, the operational speed characteristics are determined by the slowest read speed, in other words, the read time required for the memory cell array further from the output circuit determines the operational speed of the device.
Furthermore, conventional semiconductor memory devices, because of the device configuration, include the read-data multiplexers (107-e and 107-o in FIG. 10) for selecting memory cell arrays to be selected as well as the divided-data multiplexer (108 in FIG. 10) for selecting either the even data or odd data. Therefore, read-data output from the parallel-serial conversion circuits must pass through two gates before they can reach the i/o pad. For this reason, propagation delay of read-data is increased, thus contributing another reason for reducing the operational speed of the device.